1. Field of the Invention
The present invention relates to an analog signal input circuit employed in a complementary MOS integrated circuit, and more particularly to an analog signal input circuit inserted immediately before the input terminal of a device which is required of high accuracy, as in the case of an analog-to-digital converter (hereinafter referred to as an A/D converter).
2. Description of the Related Art
FIG. 3 shows a conventional analog input type multiplexing circuit employed in an A/D converter. The multiplexing circuit has a plurality of analog input terminals INl to INn. Of these analog input terminals, one is selected on the basis of selection signals CO to Cn. An analog signal is input to the multiplexing circuit through the selected analog input terminal, and is then supplied to a load connected to the output terminal of the multiplexing circuit.
In the case of an A/D converter having a plurality of analog signal input terminals, it may happen that either a voltage higher than the power source voltage or a voltage lower than the ground-level voltage will be applied to non-selected input terminals. Even if this happens, the accuracy of the A/D converter should be kept unchanged.
However, the conventional multiplexing circuit shown in FIG. 3 has problems connection with this matter. Let it be assumed that a voltage higher than the power source voltage or lower than the ground-level voltage is applied to a non-selected analog signal input terminal of the conventional multiplexing circuit. In this case, a bipolar transistor which is parasitic on the MOSFET structure at the non-selected input terminal conducts a small amount of current. This current flows to the output terminal of the multiplexing circuit, thus producing an error in the analog signal to be supplied to the A/D converter. As a result, the accuracy of the A/D converter is adversely affected. The parasitic transistor is a PNP or NPN transistor component which is undesirably formed when an MOSFET is formed.
The above-mentioned problem will be explained in more detail, with reference to FIG. 4 showing an equivalent circuit corresponding to a conventional analog signal input circuit. In the explanation below, it is assumed that the power source voltage is 5V, and the voltage applied to an input terminal is .+-.10V.
Assume that, in the circuit shown in FIG. 3, a voltage of .+-.10V is applied to input terminal INn, with an analog signal in the range of 0 to 5V supplied to input terminal INl. In this case, a current flows from input terminal INn to positive power source VDD through protective diodes, so that the potential at input terminal INn gradually becomes closer to 5V. However, since a voltage drop occurs due to diodes connected in the forward direction or due to a parasitic resistor produced in the path of current I.sub.BPl, the potential at input terminal INn is actually higher than 5V by about 0.5 to 0.6V. Therefore, parasitic bipolar transistor PNPI whose base potential is fixed to 5V becomes slightly conductive, with the result that current I.sub.CPI flows to the output terminal via an input-protecting resistor and the emitter-collector path of transistor PNPl. Accordingly, an error corresponding to current I.sub.CPl is produced in the analog signal supplied from input terminal INl to the output terminal.
A similar problem also occurs in the case where a voltage of -10V is applied to input terminal INn. In this case, the potential at input terminal INn lowers by a value corresponding to the base-emitter threshold voltage V.sub.BE of parasitic bipolar transistor NPNl (the base-emitter threshold voltage being about 0.5 to 0.6V if the parasitic bipolar transistor is a silicon transistor), so that parasitic bipolar transistor NPNl becomes slightly conductive. As a result, current ICNI, which corresponds to the positive potential of the analog signal at the output terminal, flows to input terminal INn via the emitter-collector path of bipolar transistor NPNl. As a result, the voltage of the analog signal at the output terminal cf the multiplexing circuit may be varied.